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Data Sheet
energy accumulated into the accumulator reaches one of the
WTHR, VARTHR, or VATHR thresholds, a dedicated interrupt
can be triggered synchronously with the corresponding CFx
pulse. The sign of each sum can be read in the PHSIGN register.
REACTIVE
ENERGY
NO-LOAD
THRESHOLD
REACTIVE
POWER
NO-LOAD
THRESHOLD
NO-LOAD
THRESHOLD
ACTIVE
POWER
REVRPx BIT
IN STATUS0
xVARSIGN BIT
IN PHSIGN
VARNOLOAD POS NEG POS
SIGN = POSITIVE
Figure 94. Fundamental Reactive Power Accumulation in Sign
Adjusted Mode
REACTIVE ENERGY
NO-LOAD
THRESHOLD
REACTIVE POWER
ADE7880
indicate the sign of the sum of phase powers. When cleared to
0, the sum is positive. When set to 1, the sum is negative.
Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the IRQ0 pin is set low, and the
status bit is set to 1 whenever a change of sign occurs. To find
the phase that triggered the interrupt, the PHSIGN register is
read immediately after reading the STATUS0 register. Next, the
status bit is cleared, and the IRQ0 pin is set high again by writing
to the STATUS0 register with the corresponding bit set to 1.
NO LOAD CONDITION
The no load condition is defined in metering equipment standards
as occurring when the voltage is applied to the meter and no cur-
rent flows in the current circuit. To eliminate any creep effects in
the meter, the ADE7880 contains three separate no load
detection circuits: one related to the total active power, one
related to the fundamental active and reactive powers, and one
related to the apparent powers.
No Load Detection Based On Total Active Power and
Apparent Power
This no load condition uses the total active energy and the
apparent energy to trigger this no load condition. The apparent
energy is proportional to the rms values of the corresponding
phase current and voltage. If neither total active energy nor
apparent energy are accumulated for a time indicated in the
respective APNOLOAD and VANOLOAD unsigned 16-bit
registers, the no load condition is triggered, the total active
energy of that phase is not accumulated and no CFx pulses are
generated based on the total active energy.
The equations used to compute the APNOLOAD and
VANOLOAD unsigned 16-bit values are
APNOLOAD = 2 16 ?
VANOLOAD = 2 16 ?
NO-LOAD
THRESHOLD
REVAPx BIT
IN STATUS0
xVARSIGN BIT
IN PHSIGN
Y × WTHR × 2 17
PMAX
Y × VATHR × 2 17
PMAX
(50)
VARNOLOAD
SIGN = POSITIVE
POS
NEG POS NEG
where:
Y is the required no load current threshold computed relative to
Figure 95. Fundamental Reactive Power Accumulation in Absolute Mode
Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and
REVPSUM1, respectively) of the STATUS0 register are set
to 1 when a sign change of the sum of powers in CF3, CF2,
or CF1 data paths occurs. To correlate these events with the
pulses generated at the CFx pins, after a sign change occurs,
Bit REVPSUM3, Bit REVPSUM2, and Bit REVPSUM1 are set
in the same moment in which a high-to-low transition at the
full scale. For example, if the no load threshold current is set
10,000 times lower than full scale value, then Y = 10,000.
WTHR and VATHR represent values stored in the WTHR and
VATHR registers and are used as the thresholds in the first stage
energy accumulators for active and apparent energy, respectively
(see Active Energy Calculation section). PMAX = 27,059,678 =
0x19CE5DE, the instantaneous active power computed when
the ADC inputs are at full scale.
CF3, CF2, and CF1 pin, respectively, occurs.
Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and SUM1SIGN,
respectively) of the PHSIGN register are set in the same moment
with Bit REVPSUM3, Bit REVPSUM2, and Bit EVPSUM1 and
Rev. A | Page 69 of 104
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